Sequential Logic Labs

This section covers sequential logic circuits and their implementation using Verilog on the DE10-Lite FPGA board.

Learning Objectives

• Understand latches, flip-flops, and registers
• Design sequential circuits with clock signals
• Implement shift registers and counters
• Create finite state machines (FSM)
• Interface with external components (rotary encoder)
• Design memory systems

Labs

Select a lab from the navigation menu to get started.

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Table of contents

• Lab 5A: Latches and Flip-flops
• Lab 5: Shift Logic
• Lab 6: Multiple Digit Display
• Lab 7A/7B: Rotary Encoder
• Lab 8: Memory