Combination Logic Labs

This section covers combinational logic circuits and their implementation using Verilog on the DE10-Lite FPGA board.

Learning Objectives

• Understand and implement basic logic gates in Verilog
• Write testbenches for simulation
• Design combinational circuits using Boolean algebra
• Interface with seven-segment displays
• Implement error correction codes

Labs

Select a lab from the navigation menu to get started.

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Table of contents

• Lab 1: Introduction to Verilog HDL
• Lab 2A: Introduction to Testbenches
• Lab 2: Encoder Design (ECC)
• Lab 3A: Connecting to DE10-Lite Hardware
• Lab 3: Seven Segment Display
• Lab 4: Four-bit Error Correction Code (ECC) using Hamming(7,4) Code Decoding